1. Field of the Invention
This invention relates to a high breakdown voltage semiconductor device in which a first semiconductor element with high breakdown voltage and a second semiconductor element acting as the control circuit thereof are integrally formed and more particularly to a high breakdown voltage semiconductor device in which the first semiconductor element with high breakdown voltage is formed of insulated gate bipolar transistors (IGBTs) having trench structures or the like and the control circuit is formed of a field effect transistor, bipolar transistor or the like formed of polycrystalline semiconductor.
2. Discussion of the Background
In the field of power electronics, an IGBT having a high speed switching characteristic and high power characteristic is widely used as an excellent power switching element. At the time of operation of this type of switching element, a control circuit such as a gate driver circuit or overcurrent protection circuit is simultaneously used.
Therefore, it is expected that the cost can be greatly reduced and the area of the device can be reduced by integrally and simultaneously forming the control circuit and the IGBTs.
Specifically, it is possible to form a thin film transistor (TFT) of polysilicon as the control circuit on the pads of the IGBTs with an insulating film disposed therebetween.
FIG. 1 is a cross sectional view showing the structure of a high breakdown voltage semiconductor device in which vertical IGBTs and a control circuit are integrated. In the high breakdown voltage semiconductor device, p-type impurity is selectively ion-implanted from the surface to form p-type base regions (wells) 5 by use of a resist mask. Then, a field oxide film 2 is formed by oxidation to a thickness of approximately 500 nm to 1 .mu.m on the surface of an n.sup.- -type substrate 1 formed of single crystal silicon. On the rear surface of the n.sup.- -type substrate 1, an n-type buffer layer 3 and p.sup.+ -type drain layer 4 are formed by diffusion. Then, a drain electrode 4a is formed on the rear surface of p.sup.+ -type drain layer 4.
After this, amorphous silicon is deposited on the field oxide film 2 and then the amorphous silicon is annealed to grow as a polysilicon layer 6 in a solid phase. Then, a p-type active layer 7 is formed in the polysilicon layer by ion-implantation for a channel layer. After this, gate oxide films 8, 9 and gate electrodes 10, 11 of the vertical IGBT and TFT are simultaneously formed.
Then, n.sup.+ -type source layers 12 of the vertical IGBT and an n.sup.+ -type source region 13 and n.sup.+ -type drain region 14 of the TFT are simultaneously formed in a self-alignment manner by ion-implantation using the gate electrodes 10 and 11 each as a mask. Electrodes are connected to the respective areas to complete an integrated structure of the vertical IGBTs and the control circuit.
Recently, as the IGBT, a trench structure is used instead of the planer structure described above in order to enhance the current density.
However, in order to form an IGBT of trench structure, it is required to form an n.sup.+ -type source layer on the surface of the p-type base layer, then form a trench and bury a gate electrode in the trench. On the other hand, in the TFT, a gate electrode is formed and source and drain regions are formed in a self-alignment manner with the gate electrode used as a mask. Thus, in the TFT and IGBT of the trench structure, the order in which the gate electrode and the source region are formed is reversed, it is difficult to simultaneously form them, and it is not preferable to integrally form them.